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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998, 1999 240-output lcd column (segment) driver with built-in ram data sheet mos integrated circuits m m m m pd16663 document no. s13392ej1v0ds00 (1st edition) date published december 1999 ns cp(k) printed in japan the mark h shows ma j or revised points. description the m pd16663 is a column (segment) driver device with built-in ram. it is capable of driving a full-dot lcd. there are 240 outputs that, with the 240 160 4-bit built-in display ram, enable a 16-gray scale display. the sixteen gray scales can be selected arbitrarily from a 49-stage palette. when combined with the m pd16667, this device can drive displays of 240 160 to 480 320 dots. features ? built-in display ram: 240 160 4 bits ? logic voltage: 3.0 to 3.6 v ? duty cycle: 1/160 ? number of outputs: 240 ? gray scales: 16 (selectable from a palette of 49) ? memory management: packed pixel ? compatible with 8-bit/16-bit data buses ordering information part number package m pd16663n- tcp (tab) m pd16663n-051 2-side standard tcp remark the tcp's external shape is customized. to order the required shape, please contact an nec salesperson. h
data sheet s13392ej1v0ds00 2 m m m m pd16663 block diagram dir pl0, pl1 test a 0 - a 16 rdy bmode d 0 - d 15 /refrh /reset ms osc1 osc2 /doff 3.3-v operation 5.0-v operation 3.3-v operation 5.0-v operation v 0 v 1 v 2 pulse /frm l1 l2 y 1 y 2 y 3 y 240 stb /dout control address management circuit arbiter cr oscillator gray scale generation circuit internal timing generator 240 outputs of lcd driver circuit self-diagnostic circuit gray scale control dec data latch (2) data latch (1) level shifter lcd timing generator ram 240 x 160 x 4 bits address input control data bus control stop /cs, /oe, /we, /ube pulse /frm stb remark / indicates active low signal.
data sheet s13392ej1v0ds00 3 m m m m pd16663 1. pin functions classification pin name note i/o function cpu interface d 0 to d 15 i/o data bus : 16 bits a 0 to a 1 6 i address bus : 17 bits /cs i chip select 3.3 v /oe i read signal /we i write signal /ube i upper byte enable rdy o ready signal issued to cpu ("h" sets ready status) control signals pl0 i specifies the lsi placement position (no. 0 to 3) pl1 i specifies the lsi placement position (no. 0 to 3) dir i specifies the direction of the lcd panel placement ms i selects between master/slave ("h" sets master mode) bmode i selects the data bus bit ("h" sets 8 bits, "l" sets 16 bits) 3.3 v /refrh i/o self-diagnostics reset pin (wired-or connection) test i test pin ("h" sets test mode, pull-down resistor is built-in) /reset i reset signal /doff i display off input signal osc1 - for external resistor for oscillator osc2 - for external resistor for oscillator stb i/o column driving signal (ms pin "h" sets output, ms pin "l" sets input) /frm i/o frame signal (ms pin "h" sets output, ms pin "l" sets input) 5.0 v pulse i/o 25-gray-scale pulse modulation clock l1 i/o row driver driving level select signal (line 1) l2 i/o row driver driving level select signal (line 2) /dout o display off output signal lcd drive y 1 to y 240 o lcd drive output power supply gnd - ground ( 2 for 5 v, 3 for 3.3 v) v cc1 - 5-v power supply v cc2 - 3.3-v power supply v 0 - lcd drive analog power supply v 1 - lcd drive analog power supply v 2 - lcd drive analog power supply note 3.3-v pins : d 0 to d 15 , a 0 to a 16 , /cs, /oe, /we, /ube, rdy, bmode, pl0, pl1, dir, osc1, osc2, /reset, /doff, test, ms 5-v pins :stb, /frm, l1, l2, /dout, pulse remark n.c. = non-connection
data sheet s13392ej1v0ds00 4 m m m m pd16663 2. block function (1) address management circuit converts an address transferred from the system via a 0 to a 16 to an address that corresponds to the on- chip ram memory map. this function enables address management for a display size of up to 480 x 320 dots using four m pd16663 lsis, thus facilitating the configuration of lcd systems. the allocation of addresses 1fff80h to 1fffeh (even addresses only) to the gray scale palette register also allows the user to select any 16 gray scales from a palette of 49. (2) arbiter resolves a conflict between a ram access from the system and a ram read on the lcd drive side. (3) ram 240 x 160 x 4 bits of static ram (single port). (4) data bus control controls the direction in which data is transferred according to whether the system is reading or writing. the bus width can also be switched between 8 and 16 bits with the bmode pin. (5) gray scale generation circuit culls frames and modulates the pulse width to realize 49 gray scales. (6) internal timing generator generates the internal timing for each block from the /frm and stb signals. (7) cr oscillator in master mode, this oscillator generates the clock referenced for the frame frequency. the frame frequency is determined by dividing this clock by 2592. to obtain a frame frequency of 70 hz, therefore, an oscillation frequency of 181.44 khz is required. because the cr oscillator is on chip, adjust the oscillation frequency using an external resistor. oscillation is stopped in slave mode. (8) lcd timing generator in master mode, this generator generates /frm (the frame signal), stb (the column driver signal strobe), and pulse (the 49-gray-scale pulse modulation clock). (9) gray scale control this is a circuit for realizing a 16-gray-scale display.
data sheet s13392ej1v0ds00 5 m m m m pd16663 (10) data latch (1) latches 240-pixel data read from ram. (11) data latch (2) latches 240-pixel data in synchronization with the stb signal. (12) level shifter converts the internal circuit operating voltage (3.3 v) to the voltage required by the lcd driver and row driver interface (5 v). (13) dec decodes the gray scale display data into the corresponding lcd drive voltages v 0 , v 1 , and v 2 . (14) lcd driver circuit creates the voltage to be applied to the lcd by selecting one of lcd drive power supplies v 0 , v 1 , or v 2 , according to the gray scale data and display off signal (/doff). (15) self-diagnostic circuit automatically detects any mismatch between the operation timings of the master and slave chips cause by noise, etc., and issues a refresh signal to all the column drivers. address map image (half vga size) column direction specified with a 7 to a 0 y 1 y 1 y 1 l1 l160 l1 l160 no. 0 no. 2 no. 1 no. 3 y 240 y 240 y 240 y 240 y 1 address increases in this direction address increases in this direction line direction specified with a 16 to a 8
data sheet s13392ej1v0ds00 6 m m m m pd16663 3. data bus the byte data ordering on the data bus is little endian, which is the format commonly used in most nec and intel products. (1) 16-bit data bus (bmode = l) byte access d 0 to d 7 d 8 to d 15 00000h 00001h 00002h 00003h 00004h 00005h :: address increases ? as shown :: word access d 0 to d 7 d 8 to d 15 00000h 00002h 00004h : address increases ? as shown : in the same way as access from the system can be performed in word (16-bit) and byte (8-bit) units, valid data is indicated by d 0 to d 7 and/or d 8 to d 15 , by means of the /ube signal (higher byte enable) and a 0 . i/o /cs /oe /we /ube a 0 mode d 0 to d 7 d 8 to d 15 h not selected hi-z hi-z llhl l h l h l read dout hi-z dout dout dout hi-z lhll l h l h l write din din din din l l h h h h output disable hi-z hi-z hi-z hi-z remark = don't care, hi-z= high impedance
data sheet s13392ej1v0ds00 7 m m m m pd16663 (2) 8-bit data bus (bmode = h) d 0 to d 7 00000h 00001h 00002h : address increases ? as shown : i/o /cs /oe /we mode d 0 to d 7 d 8 to d 15 h not selected hi-z note l l h read dout note lhlwrite din note l h h output disable hi-z note note when bmode = h, d 8 to d 15 can be either left open or connected to gnd because they and /ube are pulled down internally. remark = don't care, hi-z= high impedance
data sheet s13392ej1v0ds00 8 m m m m pd16663 4. relationship between data bits and pixels 16-gray scale display consists of 4 bits per pixel. in the packed pixel format, ram is configured with 2 pixels (4 pixels per word). (1) bmode = l byte (8-bit) access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 pixel 1 pixel 2 pixel 3 pixel 4 lcd panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 00000h 00001h 00002h 00003h 00004h 00005h 00006h 00007h word (16-bit) access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 pixel 1 pixel 2 pixel 3 pixel 4 lcd panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 00000h 00002h 00004h 00006h (2) bmode = h d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 pixel 1 pixel 2 pixel 3 pixel 4 lcd panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 00000h 00001h 00002h 00003h 00004h 00005h 00006h 00007h 00000h 00001h 00000h 00000h 00001h
data sheet s13392ej1v0ds00 9 m m m m pd16663 5. gray scale control gray scale control in the m pd16663 realizes a palette of 49 gray scales, generated by culling frames and modulating the pulse width. from these 49 gray scales, 16 can be selected and recorded in the gray scale palette register. 5.1 gray scale palette register the gray scale palette register is used to preselect 16 gray scales from a palette of 49. this register is allocated to addresses 1ff80h to 1fffeh (even addresses only) and has the following relationship with gray scale data. the gray scale palette register can be set according to the mapping positions of column drivers 0 to 3, as determined by pl0 and pl1.
data sheet s13392ej1v0ds00 10 m m m m pd16663 gray scale palette register (1/2) gray scale data (display data) address lsi placement position no. d 3 /d 7 d 2 /d 6 d 1 /d 5 d 0 /d 4 initial value 1ff80 h 0 0 0 0 gray scale 0 1ff82 h 0 0 0 1 gray scale 4 1ff84 h 0 0 1 0 gray scale 8 1ff86 h 0 0 1 1 gray scale 12 1ff88 h 0 1 0 0 gray scale 16 1ff8a h 0 1 0 1 gray scale 19 1ff8c h 0 1 1 0 gray scale 21 1ff8e h 0 1 1 1 gray scale 23 1ff90 h 1 0 0 0 gray scale 25 1ff92 h 1 0 0 1 gray scale 27 1ff94 h 1 0 1 0 gray scale 29 1ff96 h 1 0 1 1 gray scale 32 1ff98 h 1 1 0 0 gray scale 36 1ff9a h 1 1 0 1 gray scale 40 1ff9c h 1 1 1 0 gray scale 44 1ff9e h no. 0 1 1 1 1 gray scale 48 1ffa0 h 0 0 0 0 gray scale 0 1ffa2 h 0 0 0 1 gray scale 4 1ffa4 h 0 0 1 0 gray scale 8 1ffa6 h 0 0 1 1 gray scale 12 1ffa8 h 0 1 0 0 gray scale 16 1ffaa h 0 1 0 1 gray scale 19 1ffac h 0 1 1 0 gray scale 21 1ffae h 0 1 1 1 gray scale 23 1ffb0 h 1 0 0 0 gray scale 25 1ffb2 h 1 0 0 1 gray scale 27 1ffb4 h 1 0 1 0 gray scale 29 1ffb6 h 1 0 1 1 gray scale 32 1ffb8 h 1 1 0 0 gray scale 36 1ffba h 1 1 0 1 gray scale 40 1ffbc h 1 1 1 0 gray scale 44 1ffbe h no. 1 1 1 1 1 gray scale 48 remark the gray scale palette register is initialized by the /reset signal. h
data sheet s13392ej1v0ds00 11 m m m m pd16663 gray scale palette register (2/2) gray scale data (display data) address lsi placement position no. d 3 /d 7 d 2 /d 6 d 1 /d 5 d 0 /d 4 initial value 1ffc0 h 0 0 0 0 gray scale 0 1ffc2 h 0 0 0 1 gray scale 4 1ffc4 h 0 0 1 0 gray scale 8 1ffc6 h 0 0 1 1 gray scale 12 1ffc8 h 0 1 0 0 gray scale 16 1ffca h 0 1 0 1 gray scale 19 1ffcc h 0 1 1 0 gray scale 21 1ffce h 0 1 1 1 gray scale 23 1ffd0 h 1 0 0 0 gray scale 25 1ffd2 h 1 0 0 1 gray scale 27 1ffd4 h 1 0 1 0 gray scale 29 1ffd6 h 1 0 1 1 gray scale 32 1ffd8 h 1 1 0 0 gray scale 36 1ffda h 1 1 0 1 gray scale 40 1ffdc h 1 1 1 0 gray scale 44 1ffde h no. 2 1 1 1 1 gray scale 48 1ffe0 h 0 0 0 0 gray scale 0 1ffe2 h 0 0 0 1 gray scale 4 1ffe4 h 0 0 1 0 gray scale 8 1ffe6 h 0 0 1 1 gray scale 12 1ffe8 h 0 1 0 0 gray scale 16 1ffea h 0 1 0 1 gray scale 19 1ffec h 0 1 1 0 gray scale 21 1ffee h 0 1 1 1 gray scale 23 1fff0 h 1 0 0 0 gray scale 25 1fff2 h 1 0 0 1 gray scale 27 1fff4 h 1 0 1 0 gray scale 29 1fff6 h 1 0 1 1 gray scale 32 1fff8 h 1 1 0 0 gray scale 36 1fffa h 1 1 0 1 gray scale 40 1fffc h 1 1 1 0 gray scale 44 1fffe h no. 3 1 1 1 1 gray scale 48 remark the gray scale palette register is initialized by the /reset signal. h
data sheet s13392ej1v0ds00 12 m m m m pd16663 5.2 relationship between gray scales and gray scale palette data the relationship between the gray scales and gray scale palette data set with the gray scale palette register is shown in the table below. gray scale palette data (1/2) gray scale palette data pmode d 5 d 4 d 3 d 2 d 1 d 0 remark gray scale 0000000off gray scale 1000001 gray scale 2000010 gray scale 3000011 gray scale 4000100 gray scale 5000101 gray scale 6000110 gray scale 7000111 gray scale 8001000 gray scale 9001001 gray scale 10001010 gray scale 11001011 gray scale 12001100 gray scale 13001101 gray scale 14001110 gray scale 15001111 gray scale 16010000 gray scale 17010001 gray scale 18010010 gray scale 19010011 gray scale 20010100 gray scale 21010101 gray scale 22010110 gray scale 23010111 gray scale 24011000 gray scale 25011001 gray scale 26011010 gray scale 27011011 gray scale 28011100 gray scale 29011101 gray scale 30011110
data sheet s13392ej1v0ds00 13 m m m m pd16663 gray scale palette data (2/2) gray scale palette data pmode d 5 d 4 d 3 d 2 d 1 d 0 remark gray scale 31011111 gray scale 32100000 gray scale 33100001 gray scale 34100010 gray scale 35100011 gray scale 36100100 gray scale 37100101 gray scale 38100110 gray scale 39100111 gray scale 40101000 gray scale 41101001 gray scale 42101010 gray scale 43101011 gray scale 44101100 gray scale 45101101 gray scale 46101110 gray scale 47101111 gray scale 48110000 on
data sheet s13392ej1v0ds00 14 m m m m pd16663 6. lsi mapping and address management addresses can be managed when using up to four m pd16663 lsis, which enables the configuration of a half vga size lcd (320 x 480 dots). in this case, the data bus and /cs, /we, and /oe pins can be used commonly. the system can handle each lcd screen as a single area in memory, eliminating the need to decode multiple m pd16663 lsis. the lsi no. and layout are specified by the pl0 and pl1 pins, and the dir pin is used to determine the direction of the lcd contents (height, width). pl1 pl0 lsi placement position no. 00 no. 0 01 no. 1 10 no. 2 11 no. 3
data sheet s13392ej1v0ds00 15 m m m m pd16663 6.1 addresses for half-vga size horizontal rectangle 00000 00002 09f00 09e00 09f02 09f74 09f76 09e76 00074 00100 00076 00176 00078 0007a 09f78 09e78 09f7a 09fec 09fee 09eee 000ec 00178 000ee 001ee 0a000 0a002 13f00 13e00 13f02 13f74 13f76 13e76 0a074 0a100 0a076 0a176 0a078 0a07a 13f78 13e78 13f7a 13fec 13fee 13eee 0a0ec 0a178 0a0ee 0a1ee no.0 no.1 no.2 no.3 specified with a 7 to a 0 specified with a 16 to a 8 y 1 x 1 x 160 x 1 x 160 y 240 y 1 y 240 y5 y 240 y 1 y 240 pd16663 pd16663 pd16663 pd16663 pd16667 pd16667 m m m m m m dir = "0"
data sheet s13392ej1v0ds00 16 m m m m pd16663 6.2 addresses for half-vga size vertical rectangle 00000 00002 00074 00100 no.0 09e00 09f00 09e76 09f76 09f74 00076 00176 09f02 0a000 0a002 0a074 0a100 no.1 13e00 13f00 13e76 13f76 13f74 0a076 0a176 13f02 00078 0007a 000ec 00178 no.2 09e78 09f78 09eee 09fee 09fec 000ee 001ee 09f7a 0a078 0a07a 0a0ec 0a178 no.3 13e78 13f78 13eee 13fee 13fec 0a0ee 0a1ee 13f7a y 1 y 240 x 160 x 1 x 160 x 1 y 1 y 240 y 1 y 240 y 1 y 240 specified with a 16 to a 8 specified with a 7 to a 0 pd16667 pd16667 pd16663 pd16663 pd16663 pd16663 m m m m m m dir = "1"
data sheet s13392ej1v0ds00 17 m m m m pd16663 7. cpu interface 7.1 rdy (ready) pin functions single port ram is used as the on-chip ram in the m pd16663. the rdy pin is used to make the cpu wait, in order to prevent contention between a cpu access and a read on the lcd side. 7.1.1 timing hi-z hi-z wait ready a 0 to a 16 ,/ube /cs /oe,/we rdy wait 7.1.2 rdy pin connection the rdy pin uses a 3-state buffer. connect an external pull-up resistor to the rdy pin. when more than one m pd16663 lsi is being used, use a wired-or connection for the rdy pin of each lsi. cpu ready input pull-up resistor rdy column driver rdy column driver v cc2
data sheet s13392ej1v0ds00 18 m m m m pd16663 7.2 access timing (1) display data read timing a 16 to a 0 /ube /cs /oe rdy d 15 to d 0 hi-z hi-z dout hi-z hi-z (2) display data write timing a 0 to a 16 /ube /cs /we rdy d 15 to d 0 din hi-z hi-z (3) gray scale palette data write timing a 0 to a 16 /ube /cs /we rdy d 5 to d 0 hi-z din
data sheet s13392ej1v0ds00 19 m m m m pd16663 8. initialization function two initialization functions are available in the m pd16663. 8.1 initialization by /reset /reset is used for forcible external initialization of the lsi. when /reset = l, the internal statuses of the m pd16663 are as follows. oscillation stopped lcd timing generator initialized internal timing generator initialized self-diagnostic circuit initialized gray scale palette register initialized display off the display remains off for 4 frame cycles after /reset release, even if the /doff pin is h. /reset /frm 12345 6 /dout internal status display off display on be sure to initialize the lsi by /reset when turning on the power. 8.2 initialization by /refrh /refrh is a pin used by the internal self-diagnostic circuit to initialize the lsi when there are mismatches in the timing of the column drivers due to external noise, etc. when /refrh = l, the internal statuses of the m pd16663 are as follows. oscillation stopped lcd timing generator initialized internal timing generator initialized display off h
data sheet s13392ej1v0ds00 20 m m m m pd16663 the display remains off for 4 frame cycles after /refrh release, even if the /doff pin is h. /refrh /frm 12345 6 /dout internal status display off display on 9. display off function when /doff = l, the column driver outputs (y n ) are all at the v 1 level. moreover, because the /dout output is also l, the /doff signal of the row driver becomes l, causing all the row driver outputs (x n ) to also be at the v 1 level. the display is therefore forcibly put in the off status, regardless of the display data. remark /doff is the row driver input pin. h
data sheet s13392ej1v0ds00 21 m m m m pd16663 10. lcd timing generator circuit if master mode is entered by setting ms to h, /frm and stb are generated at a timing that is 1/160 of the duty ratio, and driver voltage selection signals l1 and l2 are generated for the row driver. /frm is generated twice per frame, stb 81 times per 1/2 frame or 162 times per frame. (1) /frm, stb signal generation osc1 pulse stb /frm stb 81 frame 1 2 81 1 2 81 1 2 12 (2) l1, l2 signal generation stb 1 2 3 4 ? 1234 ? 1234 ? 1234 ? l1 1111 ? 1111 ? 0000 ? 0000 ? l2 1010 ? 0101 ? 0101 ? 1010 ?
data sheet s13392ej1v0ds00 22 m m m m pd16663 11. self-diagnostic function this function is provided to monitor whether there are any mismatches in the timing of the column drivers due to factors such as external noise. the slave chip compares l1 and l2 of the master chip with its own internally generated l1 and l2, and if a mismatch is detected, it issues a refresh signal to all the column drivers. upon the receipt of a refresh signal, an internal reset is instigated, and the timing is initialized. at this time, the display remains off for a period equal to 4 frame cycles plus the time /refrh is l. monitoring for an l1, l2 mismatch takes place every 1/2 frame at the rising edge of /frm. l1 ( master) l2 ( master) l1 ( slave) l2 ( slave) /refrh initialization initialization mismatch mismatch block configuration (slave) self-diagnostic circuit internal reset internal l1 signal internal l2 signal l1 l2 /reset /refrh
data sheet s13392ej1v0ds00 23 m m m m pd16663 12. example system configuration the following example shows the configuration of a system using four m pd16663 lsis and two row drivers to drive a half vga size (480 x 320 dots, landscape) lcd panel. the lsi no. is set for each column driver using the pl0 and pl1 pins. the dir pin on each column driver is set to low. one of the column drivers is specified as the master; the remaining are all slaves. the master column driver supplies signals to the slave column drivers and the row drivers. an oscillator resistor is attached across the osc1 and osc2 pins of the master, while those of the slaves are left open. the signals issued by the system (d 0 to d 15 , a 0 to a 16 , /cs, /oe, /we, /ube, rdy, /reset, /doff) are connected in parallel to all the column drivers. a pull-up resistor is connected to the rdy signal. the test pin is used for testing the lsi, so either leave it open or connect it to gnd when configuring the system. y 1 y 240 y 1 y 240 y 1 160 160 y 240 y 1 y 240 scan direction scan direction rdy /doff /reset d 0 to d 15 a 0 to a 16 control /cs, /oe, /we, /ube master no.0 slave no.2 slave no.3 slave no.1 osc1 osc2 pulse stb /frm /dout,/doff l1 l2 /refrh row driver row driver v cc2 , remark the /doff pin is an input pin of row driver.
data sheet s13392ej1v0ds00 24 m m m m pd16663 13. chipset power application it is recommended that the power be applied to the chipset in the following order. v cc2 ? v cc1 ? cpu interface ? v dd , v ee ? v 1 , v 2 the lcd drive power supplies v 1 and v 2 must be applied last. v cc2 v cc1 v ee note 2 v dd note 2 v 1 v 2 cpu interface note 1 (a 0 to a 16 , /cs, /oe, /we, /ube, d 0 to d 15 , /doff) off off off off off off 0 v 0 v on on on on on on 4.5 v 3.3 v 3.3 v /reset 0.3v cc2 0 s or more 0 s or more 0 s or more 100 ns or more notes1. the select signals (pl0, pl1, dir, ms, and bmode) can be input at the same time as v cc2 . 2. v dd and v ee do not have to be on at the same time. v dd and v ee are the row driver lcd power supplies. caution turn off the power of the chipset in the reverse order to the one above.
data sheet s13392ej1v0ds00 25 m m m m pd16663 14. example of schottky barrier diode layout for power supply protection within the module (use schottky barrier diodes that are v f = 0.5 v or less.) v dd note v cc1 v 2 v 1 v 0 v ee note v ss those diodes within the dotted line must be placed when v 0 is 0 v (gnd) or less. note v dd and v ee are the row driver lcd power supplies.
data sheet s13392ej1v0ds00 26 m m m m pd16663 15. electrical specifications absolute maximum ratings (t a = +25c) item symbol rating units power supply voltage (1) note 1 v cc1 - 0.5 to +6.5 v power supply voltage (2) note 2 v cc2 - 0.5 to +4.5 v input/output voltage (1) note 1 v i/o1 - 0.5 to v cc1 + 0.5 v input/output voltage (2) note 2 v i/o2 - 0.5 to v cc2 + 0.5 v input/output voltage (3) note 3,4 v i/o3 - 0.5 to v cc1 + 0.5 v operating ambient temperature t a - 20 to +70 c storage temperature t stg - 40 to +125 c notes 1. 5-v signals (/frm, stb, /dout, l1, l2, pulse) 2. 3.3-v signals (ms, dir, pl0 to pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, osc1, osc2, /doff, test, bmode, /refrh) 3. lcd driver power supply (v 0 , v 1 , v 2 , y 1 to y 240 ) 4. ensure that v 0 < v 1 < v 2 . caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating ranges (t a = - - - - 20c to +70c, v 0 = 0 v) item symbol min. typ. max. units power supply voltage (1) v cc1 4.5 5.0 5.5 v power supply voltage (2) v cc2 3.0 3.3 3.6 v input voltage (1) note 1 v i1 0v cc1 v input voltage (2) note 2 v i2 0v cc2 v v 1 input voltage v 1 v 0 v 2 v v 2 input voltage v 2 v 1 v cc1 v osc external resistor r osc 30 62 90 k w notes 1. 5-v signals (/frm, stb, l1, l2, pulse) 2. 3.3-v signals (ms, dir, pl0 to pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, osc1, osc2, /doff, test, bmode, /refrh)
data sheet s13392ej1v0ds00 27 m m m m pd16663 dc characteristics (unless specified otherwise, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - - - - 20c to +70c) item symbol conditions min. typ. max. units high-level input voltage (1) for v cc1 note 1 v ih1 0.7v cc1 v low-level input voltage (1) for v cc1 note 1 v il1 0.3v cc1 v high-level input voltage (2) for v cc2 note 2 v ih2 0.7v cc2 v low-level input voltage (2) for v cc2 note 2 v il2 0.3v cc2 v high-level input voltage (2) for v cc2 note 4 v ih3 0.8v cc2 v low-level input voltage (2) for v cc2 note 4 v il3 0.2v cc2 v high-level output voltage (1) for v cc1 note 3 v oh1 i oh = -1 ma v cc1 - 0.4 v low-level output voltage (1) for v cc1 note 3 v ol1 i ol = 2 ma 0.4 v high-level output voltage (2) for v cc1 note 1 v oh2 i oh = -2 ma v cc1 - 0.4 v low-level output voltage (2) for v cc1 note 1, 4 v ol2 i ol = 4 ma 0.4 v high-level input voltage (3) for v cc2 note 5 v oh3 i oh = -1 ma v cc2 - 0.4 v low-level output voltage (3) for v cc2 note 5 v ol3 i ol = 2 ma 0.4 v input leakage current (1) i i1 for other than test pin, v i = v cc2 or gnd 10 m a input leakage current (2) i i2 pull-down (test pin) v i = v cc2 10 40 100 m a display current drain (1) i mas1 master, for v cc1 note 6 150 m a display current drain (2) i mas2 master, for v cc2 note 6 350 m a display current drain (3) i slv1 slave, for v cc1 note 6 100 m a display current drain (4) i slv2 slave, for v cc2 note 6 250 m a lcd driver output on resistance note 7 r on 12 k w notes 1. 5-v signals (/frm, stb, l1, l2, pulse) 2. 3.3-v signals (ms, dir, pl0, pl1, a 0 to a 16 , /cs, /oe, /we, /ube, rdy, d 0 to d 15 , /reset, /doff, test, bmode) 3. /dout pin 4. /refrh pin 5. d 0 to d 15 , rdy, osc2 pins 6. frame frequency 70 hz, no-load output, cpu not being accessed (d 0 to d 15 , a 0 to a 16 , /ube = gnd, /cs, /oe, /we = v cc2 ) 7. resistance across y pin and v pin (v 0 , v 1 , or v 2 ) when a load current (ion = 100 m a) is flowing through any one of pins y 1 to y 240 .
data sheet s13392ej1v0ds00 28 m m m m pd16663 ac characteristics 1 display data send timing (1) master mode (unless specified otherwise, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20c to +70c, frame frequency 70 hz (f osc = 181.44 khz), output load: 100 pf) item symbol conditions min. typ. max. units stb clock cycle time t cyc 87 16/f osc m s stb high level width t cwh 43 8/f osc m s stb low level width t cwl 43 8/f osc m s stb rise time t r 100 ns stb fall time t f 100 ns stb-/frm delay t psf 20 m s /frm-stb delay t pfs 20 m s stb (output) /frm (output) t f t r t pfs t psf t psf t pfs t cwl t cwh t cyc 0.9v cc1 0.9v cc1 0.1v cc1 0.1v cc1
data sheet s13392ej1v0ds00 29 m m m m pd16663 (2) slave mode (unless specified otherwise, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20c to +70c) item symbol conditions min. typ. max. units stb clock cycle time t cyc 10 m s stb high level width t cwh 4 m s stb low level width t cwl 4 m s stb rise time t r 150 ns stb fall time t f 150 ns /frm setup time t sfr 1 m s /frm hold time t hfr 1 m s stb (input) /frm (input) t f t r t hfr t sfr t sfr t hfr t cwl t cwh t cyc 0.7v cc1 0.7v cc1 0.3v cc1 0.3v cc1
data sheet s13392ej1v0ds00 30 m m m m pd16663 (3) items common to both master and slaves (unless specified otherwise, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20c to +70c) item symbol conditions min. typ. max. units output delay (l1, l2, /dout) t dout1 no-load output 50 100 ns output delay (y 1 to y 240 )t dout2 no-load output 90 150 ns 0.9v cc1 stb (output) l1, l2 /dout y 1 to y 240 t dout2 t dout2 t dout1 t dout1 0.9v 2 0.9v cc1 0.1v 2 0.9v 2 0.1v 2
data sheet s13392ej1v0ds00 31 m m m m pd16663 ac characteristics 2 drawing access timing (unless specified otherwise, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v, v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20c to +70c, t r = t f = 5 ns) item symbol conditions min. typ. max. units /oe//we recovery time t ry 30 ns address setup time t as 10 ns address hold time t ah 20 ns rdy output delay time t ryr cl = 15 pf 30 ns rdy float time note 3 t ryz 30 ns wait status time note 1 t ryw 35 ns ready status time (no contention) note 1 t ryf1 60 100 ns ready status time (contention) note 1 t ryf2 650 1,200 ns data access time (read cycle) note 2 t acs 100 ns data float time (read cycle) note 3 t hz 40 ns /cs-/oe time (read cycle) t csoe 10 ns /oe-/cs time (read cycle) t oecs 20 ns write pulse width 1 (write cycle 1) note 1 t wp1 50 ns write pulse width 2 (write cycle 2) note 1 t wp2 50 ns data setup time (write cycle 1, 2) t dw 20 ns data hold time (write cycle 1, 2) t dh 20 ns /cs-/we time (write cycle 1, 2) t cswe 10 ns /we-/cs time (write cycle 1, 2) t wecs 20 ns reset pulse width t wres 100 ns rdy-/oe time t rdoe note 4 - rdy-/we time t rdwe note 4 - notes 1. load circuit 1.0 k w 1.8 k w v cc2 60 pf 2. load circuit 1.0 k w 1.8 k w v cc2 100 pf
data sheet s13392ej1v0ds00 32 m m m m pd16663 3. load circuit 1.0 k w 1.8 k w v cc2 5 pf 4. if the time from the rising edge of rdy to /oe or /we is long, the display may be adversely affected. it is therefore recommended that t rdoe and t rdwe be set to a value not exceeding 1000 ns. /oe, /we recovery time /oe,/we t ry 0.7 v cc2 read cycle a 16 to a 0 /ube /cs /oe rdy d 15 to d 0 t as t csoe t ryr t ryf t acs t hz t ryw t rdoe t ah out hi- z 0.3 v cc2 0.1v cc2 0.1 v cc2 0.9 v cc2 0.3 v cc2 0.3 v cc2 0.7 v cc2 0.7 v cc2 t ryz 0.1 v cc2 t oecs
data sheet s13392ej1v0ds00 33 m m m m pd16663 write cycle 1 (display data write) a 16 to a 0 /ube /cs /we rdy d 15 to d 0 t as t cswe t ryr t ryf t wp1 t dw t dh t ryw t rdwe t wecs t ah in hi- z 0.3 v cc2 0.1 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 0.7 v cc2 0.7 v cc2 t ryz 0.1 v cc2 write cycle 2 (gray scale palette data write) a 16 to a 0 /ube /we rdy d 15 to d 0 hi- z t as t cswe t wp2 t wecs t ah 0.3v cc2 /cs 0.7v cc2 0.3v cc2 0.7v cc2 0.3v cc2 0.7v cc2 in 0.3v cc2 t dh t dw
data sheet s13392ej1v0ds00 34 m m m m pd16663 reset pulse width t wres /reset 0.3v cc2 ac characteristics 3 cr oscillator (v cc2 = 3.0 to 3.6 v, t a = - 20c to +70c) item symbol conditions min. typ. max. units oscillation frequency f osc external resistor (62 k w ) 160 190 220 khz frame frequency - ext ernal resistor (62 k w ) 61.7 73.3 84.9 hz relationship between oscillation frequency and frame frequency / stb frequency the relationship between the oscillation frequency and the frame frequency / stb frequency is as follows. frame frequency = oscillation frequency stb frequency = oscillation frequency 1 162 2 8 1 2 8
data sheet s13392ej1v0ds00 35 m m m m pd16663 16. package drawings standard tcp package drawings ( m m m m pd16663n-051) (1/3)
data sheet s13392ej1v0ds00 36 m m m m pd16663 standard tcp package drawings ( m m m m pd16663n-051) (2/3) test pad details 0.3 0.15 0.3 0.15 0.3 0.15 0.95 0.24 0.35 0.35 p0.2 26.5 from pc from pc 16.25 16.25 0.4 0.015 0.6 0.015 alignment details 0.6 0.05 0.05 0.02 0.3 0.05 0.05 0.02 0.6 0.05 0.05 0.02 0.05 0.02 0.6 0.05 right and left center tcp tape winding direction wind-up direction the cu pattern side is the underside of the tape. output lead
data sheet s13392ej1v0ds00 37 m m m m pd16663 standard tcp package drawings ( m m m m pd16663n-051) (3/3) pin connection diagram n.c. n.c. n.c. y1 y2 y3 y118 y119 y120 n.c. n.c. n.c. n.c. y121 y122 y123 y238 y239 y240 n.c. n.c. n.c. n.c. v 0 v 1 v 2 gnd v cc1 l1 l2 /dout stb /frm pulse gnd v cc2 ms bmode test /doff rdy /we /oe /cs /ube /reset /refrh pl1 pl0 dir gnd osc2 osc1 v cc2 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd v cc2 gnd v cc1 v 2 v 1 v 0 n.c. no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.9 no.10 no.11 no.12 no.13 no.14 no.15 no.16 no.17 no.18 no.19 no.20 no.21 no.22 no.23 no.24 no.25 no.26 no.27 no.28 no.29 no.30 no.31 no.32 no.33 no.34 no.35 no.36 no.37 no.38 no.39 no.40 no.41 no.42 no.43 no.44 no.45 no.46 no.47 no.48 no.49 no.50 no.51 no.52 no.53 no.54 no.55 no.56 no.57 no.58 no.59 no.60 no.61 no.62 no.63 no.64 no.65 no.66 no.67 no.68 no.69 no.70 no.71 no.72 no.73 no.1 no.2 no.3 no.4 no.5 no.6 no.121 no.122 no.123 no.124 no.125 no.126 no.127 no.128 no.129 no.130 no.245 no.246 no.247 no.248 no.249 no.250 die : face down
data sheet s13392ej1v0ds00 38 m m m m pd16663 [memo]
data sheet s13392ej1v0ds00 39 m m m m pd16663 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd16663 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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